A core technique for modern communication systems is frequency (and/or clock) synthesis, and the phase-locked loops (hereinafter, PLL) have been widely employed in frequency synthesis. The PLL is basically a self-correcting control system in which one signal chases another signal. For example, the PLL can synchronize frequency of a voltage-controlled oscillator (hereinafter, VCO) to a reference clock signal (hereinafter, FREF) through feedback. The frequency and phase of the output clock generated from the PLL are very stable. Recently, digital PLLs (hereinafter, DPLL) have been implemented and adopted in digital communications.
Many DPLLs rely on a time-to-digital converter (hereinafter, TDC) to perform phase detection. In general, the TDC quantizes time difference between two input signals, a reference clock signal (FREF) and a variable clock (CKV), and accordingly generates a difference signal. Basically, the detected result and the output of the TDC may dominate the adjustment of a digitally controlled oscillator (hereinafter, DCO). Thus, the TDC is a critical component in DPLL, and ensuring linearity, precision and resolution of the TDC becomes an important issue.